The present invention relates to the field of integrated circuit design and semiconductor chip fabrication. More particularly, the present invention relates to a die pad fracture propagation system and method for integrated circuit chip fabrication.
Electronic systems and circuits have made a significant contribution towards the advancement of modem society and are utilized in a number of applications to achieve advantageous results. Electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include integrated circuits comprising semiconductor chips.
Typically semiconductor chip fabrication includes processes in which materials of varying conductive characteristics are layered on top of one another. These layers of different materials form electrical devices and paths through which electrical signals are propagated. As with most electrical devices, it is important that the electrical signals follow certain paths in order for theses semiconductor chips to operate correctly. Otherwise detrimental short circuits or other problems may arise. For example, most semiconductor chips have specific vias for electrical signals to travel between layers and electrical signals propagating between layers outside these vias result in short circuits preventing the semiconductor chip from operating correctly.
FIG. 1 is an illustration of a prior art semiconductor chip 100. Semiconductor chip 100 comprises substrate layer 105, a first metal layer 110, intermetal oxide (IMO) layer 115, a second metal layer 120, IMO layer 125, a third metal layer 130, passivation 107 and vias 191, 192 and 193. First metal layer 110 is coupled to substrate layer 105 and IMO layer 115 which is coupled to second metal layer 120. Third metal layer 130 is coupled to bonding ball 103, passivation 107 and IMO layer 125 which is coupled to second metal layer 120. Bonding ball 103 is coupled to wire 101 and passivation 107. In one example of semiconductor chip 100 substrate layer 105 comprises silicon (Si) and metal layers 110, 120 and 130 comprise aluminum (Al). Vias 191 and 192 are coupled to first metal layer 110 and second metal layer 120. Via 193 is coupled to second metal layer 120 and third metal layer 130.
The varying material in the different layers of semiconductor chip 100 are used to form electrical devices. For example the varying configurations of conductive material laid down in first metal layer 110, second metal layer 120 and third metal layer 130 are laid down in patterns that form transistor switches. Vias 191 and 192 provide appropriate and planned conductive paths between first metal layer 110 and second metal layer 120. Via 193 provides an appropriate and planned conductive path between second metal layer 120 and third metal layer 130. However, semiconductor chip 100 does not operate properly because fracture or crack 198 permits electrical signals to travel between the layers of semiconductor chip 100.
Crack 198 in semiconductor chip 100 occurred during the coupling of bonding ball 103 and wire 101 to third metal layer 130. Third metal layer 103 acts as a bond pad for wire 101 which is electrically coupled and attached by bonding ball 103. Bonding ball 103 is applied to third metal layer 103 and wire 101 by a wire bond process (e.g., thermal bonding, thermal sonic bonding, ultrasonic bonding, etc.). In a wire bond process the bonding ball 103 is actually formed from the wire (e.g., a gold wire) as it is extruded from a capillary tube. An electrical arch is applied to a portion of the wire as it is extruded and a ball of the wire material is created on the end of the wire. The ultrasonic waves are directed at the bonding ball which cause it to bond wire 103 to third metal layer 101. These ultra sonic waves also cause stresses in the layers of semiconductor chip 100 which result in the inappropriate and unplanned cracks or fractures.
What is required is a fabrication system and method that minimizes the spread of cracks between layers of an integrated circuit chip. The system and method should reduce the propagation of inappropriate cracks that occur between layers of a integrated circuit chip as a result of stress energy. For example the system and method should reduce the extension of fractures from one layer to another layer caused during ultrasonic bonding of a wire to bond pads of an integrated circuit chip.
The system and method of the present invention minimizes the spread of cracks between layers of an integrated circuit chip. The system and method of the present invention reduces the propagation of inappropriate cracks that occur between layers of a integrated circuit chip as a result of stress energy. The tendency of fractures caused during ultrasonic bonding of a wire to bond pads of the semiconductor chip to extend from one layer to another layer is reduced by the present invention. The present invention also permits denser bond pad packing and effectively increases die yields per wafer.
In one embodiment of the present invention a die pad crack absorption integrated circuit chip fabrication process enables a modulous stress absorbing filler layer to be included in a semiconductor chip. The modulous stress absorbing filler layer is included in the chip in a manner that reduces the spread of cracks or fractures between layers of electrically active regions in and on an integrated circuit chip. The modulous stress absorbing filler layer includes material with more enhanced elastic characteristics than the surrounding IMO layer material. The discontiguous modular elastic material absorbs energy associated with stresses applied to the integrated circuit chip thereby reducing the dissemination of fractures between layers of a die pad crack absorption integrated circuit chip.